This invention relates to field effect transistors and, more particularly, to the integration of thin film vertical gate field effect transistors into an actively addressable liquid crystal array.
In the field of flat displays, liquid crystal (LC) arrays have much to recommend them, particularly in that the picture elements or pixels can be very small, one million or more on one substrate, and that pixels and their associated charging transistors can be fabricated on the substrate in one series of known processes. However, these processes are not necessarily without problems due, for example, to the high degree of precision required in the photolithographic processes where an error of a micrometer (micron) or less could make a transistor stay on or off permanently. Since a yield of essentially 100% is required in order to have no apparent defects in the display, such a high requirement for accuracy is not economically feasible.
Most prior art displays have utilized lateral channel thin-film transistors (TFT's) to control the charge which turns on the corresponding liquid crystal element. The usual design has one connection for supplying a voltage to all transistor gates in each row, and a connection for all sources in each column. Thus, by applying the proper voltages to the appropriate row and column, each transistor can be addressed individually for charging the pixel capacitor. This capacitor is usually formed by transparent conductive elements on either side of the liquid crystal material and, when activated by the associated transistor, creates within the pixel the degree of transparency desired. In addition to the problems of the lithography as noted above, lateral devices suffer from an inherent limitation on dynamic performance; i.e. low operation speed (an upper limit of a few hundred kHz).
It will be apparent to those skilled in the art that the required speed of operation increases with the number of pixels in the array. The speed can be improved by increasing the supply voltage and improving the quality of the amorphous silicon material itself, however, the main reason for the limited speed of operation is the length of the channel, typically 5-10 .mu.m. The minimum length is, as is known, a function of the precision of the photolithography, specifically, the accuracy of the definition of the source and drain. A typical example of this type of array design is found in U.S. Pat. No. 4,621,260, to Suzuki et al. This type of array will be discussed further hereinbelow.
In an attempt to improve the speed of operation of amorphous silicon (a-Si:H) field-effect transistors, a different arrangement of the transistor elements has been developed, as noted in "Proposed Vertical-Type Amorphous Silicon Field-Effect Transistors", by Y. Uchida, Y. Nara and M. Matsumuru, in the IEEE Electron Device Letters, Vol. EDL-5, No. 4, April 1984. In this device, the source is positioned above the drain with the gate on the vertical sidewall. Such transistors are sometimes termed "edge channel" transistors. The channel length can therefore be as small as 1 .mu.m or even less; i.e. the length is the thickness of a deposited a-Si:H layer. Since an essential part of an LC array is the peripheral circuitry, such as inverters, shift registers, buffer drivers and other logic elements, it would be highly desirable to be able to fabricate all necessary devices in the same series of steps. This would eliminate the need for wire bonding chips, etc. While the use of vertical channel/gate TFTs has been previously suggested for use in liquid crystal arrays, there is no known array structure which takes full advantage of the virtues of such transistors, integrating the switching transistors and peripheral elements into the array in one series of processing steps while also minimizing the required area on the substrate.